In this paper a novel architecture of ASIP for a reconfigurable FFT is proposed. The proposed design implements a ASIP for reconfigurable 64 point FFT processor with a high speed. Hence design of reconfigurable FFT processor is proposed which can be used for various ASIPs.ASIPs are widely 3G cellular systems,wireless communication,OFDMA,ECG. The method optimizes the processing, by wiping out the non-trivial complex multiplication with the twiddle factors and fulfills the processing with no complex multiplication. is defined constant fixed for every Butterfly stage which act as Twiddle factor multiplier. To reduce the complexity of the multiplication, proposed method can be used which replaces the expensive complex multiplications with real and constant multiplications. Proposed design implements DIF-FFT algorithm using VHDL language and Xilinx 9.1i for simulation results.
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